1. Field of the Invention
The present invention relates generally to integrated circuit memory devices, and more specifically to a structure for utilizing a cache memory having faulty bits.
2. Description of the Prior Art
During the manufacture of integrated circuit memory devices, die are often discarded because certain bits of the die are defective and not easily identified and repaired at, for instance, laser repair. Even though a majority of the die may be fully functional, it is often necessary to discard the entire die as scrap if the unfunctional bits of the die are not identifiable. This problem is exacerbated when a memory device is embedded in another, more expensive device such as a microprocessor or an application specific integrated circuit (ASIC). It is undesirable to discard a costly microprocessor, for instance, just because the memory embedded in it has isolated, faulty bits. This concern for recovering the use of an integrated circuit memory die extends to technologies such as cache memories, memory cards, and memories embedded in ASICs.
Cache memories are increasingly used as primary caches embedded in high performance microprocessors or as secondary caches external to the microprocessor. As computer microprocessors have become faster and faster, the rate at which requested data must be supplied increases as well. Such memories are often used to quickly supply data requested by a microprocessor. Cache memories are an element of the typical cache system which has five elements: the microprocessor, main memory, the tag Random Access Memory (RAM), the cache memory, and control logic. The cache memory can be embedded in the microprocessor, in which case it is a "primary cache", or it may be a discrete component, external to the microprocessor, in which case it is called a "secondary cache". The tag RAM holds the address locations of all data which is stored in the data cache. The tag may be associated with a "line" of data in the cache memory, where the line is a block of data which can be one or several consecutive bytes or words of data. When the microprocessor requests information, a read signal is immediately sent to both the main memory and the tag RAM. The tag RAM compares the requested memory address with the memory address of all data stored in the cache memory. If the requested memory address is in the tag RAM, a "hit" condition exists, and data from that location will be gated from the cache memory to the microprocessor.
In a "hit" condition, the tag RAM generates a valid compare Match output signal. In the hit condition, the cache memory gates the required data onto the data bus before the main memory can respond. In this way, microprocessor wait states are avoided. However, if the tag RAM's comparison operation indicates that the desired data is not stored inside the cache memory, a "miss" condition exists, and the data must come from main memory which typically holds more data than the cache memory and is therefore much slower. As a result, the microprocessor may have to wait for several cycles, during which time it is idle, before receiving requested data from slow main memory. These unproductive cycles are referred to as "wait states" since the microprocessor must wait until the requested data is provided from main memory.
A cache memory, having randomly occurring bit(s) failures which are not easily detected and bypassed, is often discarded. Unfortunately, memory devices may suffer from high, but random, incidences of isolated bit failures due to randomly occurring process problems such as particle defects. These failures may not be easily repaired, especially if no row or column redundancy testing is employed. Even when redundancy testing at laser repair is used, this technique may not be sufficient to ferret out all such random failures. When a cache memory having bit(s) failures is resident in microprocessors, ASICs, or other devices, the faulty cache memory, along with the expensive fully functional device in which it is embedded, is often discarded. Therefore, there is an unmet need in the art to compensate for random bit(s) failures in cache memories such that they are rendered usable. It would be desirable to bypass defective data locations in the cache memory such that a cache memory and any device in which it is embedded is not scrapped.